Timing violations due to VDD/VSS bounce

Eireiner, M.; Henzler, S.; Berthold, J.; Pacha, C.; Georgakos, G.; Schmitt-Landsiedel, D.

The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

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Eireiner, M. / Henzler, S. / Berthold, J. / et al: Timing violations due to VDD/VSS bounce. 2006. Copernicus Publications.

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