An 8 bit current steering DAC for offset compensation purposes in sensor arrays

Bertotti, G.; Laifi, A.; Di Gioia, E.; Masoumi, M.; Dodel, N.; Scarselli, E. F.; Thewes, R.

An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DNL < 0.4 LSB, respectively. Static power consumption with the outputs operated at a voltage of 0.9 V is approximately 10 μW. Dynamic power, mainly consumed by switching activity of the digital circuit parts, amounts to 100 μW at 2.6 MHz operation frequency. Total area is 38.6 × 2933.0 μm 2.

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Bertotti, G. / Laifi, A. / Di Gioia, E. / et al: An 8 bit current steering DAC for offset compensation purposes in sensor arrays. 2012. Copernicus Publications.

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