Modeling of temperature scenarios in a multicore processor system
In modern CMOS integrated Systems-on-Chip global temperature variations arise as well as local fluctuations in regions of high activity, resulting in the arise of local hot spots. This in turn can greatly affect reliability and life-time of a chip. Economically affordable processor packaging cannot be provided for the worst case hot spot scenario. In a multicore system a reciprocal influence between the temperatures of neighbouring cores occur leading to increasing core temperature compared to a single core. This results in the need to monitor and regulate the operating temperature during runtime in order to keep it at tolerable values. This can be done in an easy way in an invasive architecture. In this paper the temperature distributions of cores in a multicore system are simulated for various scenarios. Different task allocation techniques and application characteristics as well as different physical conditions such as package types, material parameters and cooling all result in different system power scenarios. The impact of different scenarios which affect the system temperature scenario is investigated. The results are analysed and compared to determine the worst case scenario. With regard to simulation results and practicability the best temperature levelling measures are chosen.