A code-aided synchronization IP core for iterative channel decoders
Synchronization and channel decoding are integral parts of each receiver in wireless communication systems. The task of synchronization is the estimation of the general unknown parameters of phase, frequency and timing offset as well as correction of the received symbol sequence according to the estimated parameters. The synchronized symbol sequence serves as input for the channel decoder. Advanced channel decoders are able to operate at very low signal-to-noise ratios (SNR). For small values of SNR, the parameter estimation suffers from increased noise and impacts the communication performance. To improve the synchronization quality and thus decoder performance, the synchronizers are integrated into the iterative decoding structure. Intermediate results of the channel decoder after each iteration are used to improve the synchronization. This approach is referred to as code-aided (CA) synchronization or turbo synchronization.
A number of CA synchronization algorithms have already been published but there is no publication so far on a generic hardware implementation of the CA synchronization. Therefore we present an algorithm which can be implemented efficiently in hardware and demonstrate its communication performance. Furthermore we present a high throughput, flexible, area and power efficient code-aided synchronization IP core for various satellite communication standards. The core is synthesized for 65 nm low power CMOS technology. After placement and routing the core has an area of 0.194 mm 2, throughput of 207 Msymbols/s and consumes 41.4 mW at 300 MHz clock frequency. The architecture is designed in such a way that it does not affect throughput of the system.