High-Speed Serializer for a 64 GS s −1 Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

Widmann, Daniel; Grözing, Markus; Berroth, Manfred

An attractive solution to provide several channels with very high data rates of tens of Gbit sinline-formula−1 for digital-to-analog converters (DACs) in arbitrary waveform generators (AWGs) is to use a high speed serializer in front of the DAC. As data sources, on-chip memories, digital signal processors or field-programmable gate arrays can be used. Here, we present a serializer consisting of a 19 channel inline-formula16:1 multiplexer (MUX) for output data rates up to 64 Gbit sinline-formula−1 per channel and a low skew (inline-formula∼ 8.8 inline-formulaps) two-phase frequency divider and clock distribution network that is completely realized in static CMOS logic. The circuit is designed in a 28 inline-formulanm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology and will be used in an 8 inline-formulabit 64 GS sinline-formula−1 DAC between the on-chip memory and the DAC output stage. Due to a four bits unary and four bits binary segmentation, a 19 channel MUX is required. Simulations on layout level reveal a data-dependent peak-to-peak jitter of less than 1.8 inline-formulaps at the output of one MUX channel with a total average power consumption of approximately 1.15 inline-formulaW of the whole MUX and clock network.



Widmann, Daniel / Grözing, Markus / Berroth, Manfred: High-Speed Serializer for a 64 GS s−1 Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology. 2018. Copernicus Publications.


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