A digital receiver signal strength detector for multi-standard low-IF receivers

Saalfeld, Tobias; Piwczyk, Tobias; Wunderlich, Ralf; Heinen, Stefan

This paper presents a receiver signal strength detector based on a discrete Fourier transform implementation. The energy detection algorithm has been designed and measured using a custom multi-standard transceiver ASIC with a low-IF receiver at 0.5, 1 and 2 inline-formulaMHz IF. The proposed implementation directly processes the single bit inline-formulaΔΣ modulator data and features a clear channel assessment for arbitrary modulation schemes without energy consuming demodulation. Continuous monitoring of the derivative of the RSSI takes advantage of faster coefficient convergence for higher power levels and reduces computation time. A dynamic range of 65 inline-formuladB has been achieved in FPGA based measurements with a linearity error of less than 1.2 inline-formuladB. Furthermore, synthesis results for an on-chip implementation for an 130 inline-formulanm RF CMOS technology show an overall power consumption of 1.5 inline-formulamW during calculation.

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Saalfeld, Tobias / Piwczyk, Tobias / Wunderlich, Ralf / et al: A digital receiver signal strength detector for multi-standard low-IF receivers. 2018. Copernicus Publications.

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Rechteinhaber: Tobias Saalfeld et al.

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